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es_lpc185x/3x/2x/1x flash errata sheet lpc185x, lp c183x, lpc182x, lpc181x flash-based devices rev. 2.1 ? 23 november 2012 errata sheet document information info content keywords lpc1857fet256; lpc1857jet256; lpc1857jbd208; lpc1853fet256; lpc1853jet256; lpc1853jbd208; lpc1837fet256; lpc1837jet256; lpc1837jbd144; lpc1837jet100; lp c1833fet256; lpc1833jet256; lpc1833jbd144; lpc1833jet100; lp c1827jbd144; lpc1827jet100; lpc1825jbd144; lpc1825jet100; lp c1823jbd144; lpc1823jet100; lpc1822jbd144; lpc1822jet100; lp c1817jbd144; lpc1817jet100; lpc1815jbd144; lpc1815jet100; lp c1813jbd144; lpc1813jet100; LPC1812JBD144; lpc1812jet100 flash-based devices errata abstract this errata sheet describes both the known functional problems and any deviations from the electrical specific ations known at t he release date of this document. each deviation is assigned a number and its history is tracked in a table.
es_lpc185x_3x_2x_1x_flash all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. errata sheet rev. 2.1 ? 23 november 2012 2 of 11 contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors es_lpc185x/3x/2x/1x flash errata sheet lpc185x/3x/2x/1x flash-based devices revision history rev date description 2.1 20121123 ? added clarification that this errata applies to flash-based devices only. ? filename changed from es_lpc185x_3x_2x_1x to es_lpc185x_3x_2x_1x_flash. 2 20121031 ? added irc.1. ? removed aes.1, etm.1, rgu.1 and spifi.1; documented in user manual. ? updated eeprom.1, c_can.1 and ibat.1. ? added lpc183x, lpc182x, and lpc181x devices. ? document title changed from es_lpc1857_53 to es_lpc185x_3x_2x_1x. 1.1 20120808 ? added rgu.1 and eeprom.1. ? corrected c_can0/c_can1 peripheral assignment. 1 20120717 ? initial version.
es_lpc185x_3x_2x_1x_flash all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. errata sheet rev. 2.1 ? 23 november 2012 3 of 11 nxp semiconductors es_lpc185x/3x/2x/1x flash errata sheet lpc185x/3x/2x/1x flash-based devices 1. product identification the lpc185x/3x/2x/1x flash-based devices (hereafter referred to as ?lpc185x?) typically have the following top-side marking: lpc185xxxxxxx xxxxxxxx xxxyywwxr[x] the last/second to last le tter in the last line (f ield ?r?) will identify t he device revision. this errata sheet covers the fo llowing revisions of the lp c185x flash-based devices: field ?yy? states the year the device was manufactured. field ?ww? states the week the device was manufactured during that year. 2. errata overview table 1. device revision table revision identifier (r) revision description ?-? initial device revision table 2. functional problems table functional problems short description revision identifier detailed description c_can.1 writes to can registers write through to other peripherals ?-? section 3.1 eeprom.1 limited eeprom retention and endurance ?-? (with date code <1242) section 3.2 mcpwm.1 mcpwm abort pin not functional ?-? section 3.3 pmc.1 pmc.x power management controller fails to wake up from deep sleep, power down, or deep power down ?-? section 3.4 table 3. ac/dc deviations table ac/dc deviations short description product version(s) detailed description ibat.1 vbat supply current higher than expected ?-? section 4.1 irc.1 irc frequency variation higher than expected ?-? section 4.2 table 4. errata notes table errata notes short description revision identifier detailed description n/a n/a n/a n/a
es_lpc185x_3x_2x_1x_flash all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. errata sheet rev. 2.1 ? 23 november 2012 4 of 11 nxp semiconductors es_lpc185x/3x/2x/1x flash errata sheet lpc185x/3x/2x/1x flash-based devices 3. functional problems detail 3.1 c_can.1: writes to can registers write thro ugh to other peripherals introduction: controller area network (can) is the definition of a high performance communication protocol for serial data communication. the c_ can controller is designed to provide a full implementation of the can protocol accordin g to the can specification version 2.0b. the c_can controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a very high level of security. problem: on the lpc185x flash-based devices, there is an issue with the c_can controller ahb bus address decoding that applies to both c_can controllers. it affects the c_can controllers when peripherals on the same bus are used. writes to the adc, dac, i2c, and i2s peripherals can update registers in the c_ca n controller. specifically, writes to i2c0, mcpwm, and i2s can affect c_can1. writes to i2c1, dac, adc0, and adc1 can affect c_can0. the spurious c_can controller writes will occur at the addres s offset written to the other peripherals on the same bus. for exam ple, a write to adc0 cr register which is at offset 0 in the adc, will result in the same va lue being written to the c_can0 cntl register which is at offset 0 in the c_can controller. writ es to the c_can controller will not affect other peripherals. work-around: workarounds include: using a different c_ca n peripheral. periphera ls i2c1, dac, adc0, and adc1 can be used at the same time as c_can1 is active wit hout any interference. the i2c0, mcpwm, and i2s peripherals can be used at the same time as c_can0 is active without any interference. another workar ound is to gate the register clock to the can peripheral in the ccu. this will prevent any writes to other peri pherals from taking effect in the can peripheral. however, gating the can clock will prevent the can peripheral from operating and transmitting or receiving messages. this workaround is most useful if your applicat ion is modal and can switch between different modes such as an i2s mode and a can mode. another workaroun d is to avoid writes to the peripherals while can is active. for example, the adc coul d be configured to sample continuously or when triggered by a timer, before the can is configured. afterwards, c_can0 can be used since the adc will operate without requiring additional writes.
es_lpc185x_3x_2x_1x_flash all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. errata sheet rev. 2.1 ? 23 november 2012 5 of 11 nxp semiconductors es_lpc185x/3x/2x/1x flash errata sheet lpc185x/3x/2x/1x flash-based devices 3.2 eeprom.1: limited eeprom retention and endurance introduction: the lpc185x flash-based devices contain a 16384 byte eepr om memory with endurance of > 100 k erase / program cycles. problem: on the lpc185x flash-based lbga device s with date code <124 2, eeprom endurance and retention may be less than specified. a ll newer devices will have fully tested eeproms. work-around: using longer eeprom write ti mes will increase retention.
es_lpc185x_3x_2x_1x_flash all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. errata sheet rev. 2.1 ? 23 november 2012 6 of 11 nxp semiconductors es_lpc185x/3x/2x/1x flash errata sheet lpc185x/3x/2x/1x flash-based devices 3.3 mcpwm.1: mcpwm abort pin is not functional introduction: the motor control pwm engine is optimized for three-phase ac and dc motor control applications, but can be used in many othe r applications that need timing, counting, capture, and comparison. the mcpwm contains a global abort input that can force all of the channels into a passive state and cause an interrupt. problem: the mcpwm abort input is not functional. work-around: the mcpwm abort function can be emulated in software with the use of a non-maskable interrupt combined with an interrupt handler that shuts down the pwm. this will result in a small delay on the or der of 50 main clock cycles or about 1/3 of a microsecond at 150 mhz. alternatively, the state configur able timer (sct) can be configured to implement mcpwm functionality including an abort input. the sct can respond to external inputs in one clock cycle.
es_lpc185x_3x_2x_1x_flash all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. errata sheet rev. 2.1 ? 23 november 2012 7 of 11 nxp semiconductors es_lpc185x/3x/2x/1x flash errata sheet lpc185x/3x/2x/1x flash-based devices 3.4 pmc.1: pmc.x power management controller fails to wake up from deep sleep, power down, or deep power down introduction: the pmc implements the control sequences to enable transitioning between different power modes and controls the power state of each peripheral. in addition, wake-up from any of the power-down modes based on hardware events is supported. problem: when the chip is in a transition from active to deep sleep, power down, or deep power down, wakeup events are not captured and they will block fu rther wakeup events from propagating. the time window for this transition is 6 us and is not affected by the chip clock speed. after a wakeup event is received during the pmc transition, the chip can only recover by using an external hardware reset or by cycling power. work-around: make sure that a wakeup signal is not received during the deep sleep, power down, or deep power down transition period. an example circuit to work around this could include an external 6 us one shot which could be triggered via software using a gpio line when entering deep sleep, power down, or deep power down mode. the one-shot's output could be used to gate the wakeup signal(s) to prevent receiving a wakeup signal during the pmc transition period. depending on the system design, it may also be needed to latch the wakeup signal(s) so that they will still be pres ent after the one -shot's 6 us timeout. fig 1. pmc wakeup keep-out area pmc state run mode low power mode 6 us pmc software trigger pmc transition period wakeup signal asserted (ok) keep-out area
es_lpc185x_3x_2x_1x_flash all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. errata sheet rev. 2.1 ? 23 november 2012 8 of 11 nxp semiconductors es_lpc185x/3x/2x/1x flash errata sheet lpc185x/3x/2x/1x flash-based devices 4. ac/dc deviations detail 4.1 ibat.1: vbat supply current higher than expected introduction: the lpc185x flash-based devices contain a real-time clock which measures the passage of time. the rtc has an ultra-low power design to support battery powered systems with a dedicated battery supply pin. problem: on the lpc185x flash-based devices, high current consumption of about 70 ua or higher may occur on the vbat power supply pin due to current drain from the rtc_alarm and sample pins. on the lpc185x flash-based device s, at temperatures lower than 0 ? c, high current consumption up to 25 ua may occur on the vbat power supply pin while vdd is present if vdd < vbat. this is seen during deep sleep, power down, and deep power down modes. work-around: vbat current consumption due to rtc_alarm and sample pins can be lowered significantly by configuring the rtc_alar m pin and sample pins as "inactive" by setting the alarmctrl 7:6 field in creg0 to 0x3 and the samplectrl 13:12 field in creg0 to 0x3. these bits persist through po wer cycles and reset, as long as vbat is present. to work-around the current consumption at temperatures less than 0 ? c, keep the vbat voltage less than vdd. for example, use a 3.0 v vbat voltage with a 3.3 v vdd supply. this also avoids current consumption during active mode which can occur when vbat > vdd (see datasheet for details). 4.2 irc.1: irc frequency var iation higher than expected introduction: the irc is used as the clock source for the wwdt and/or as the clock that drives the plls and the cpu. the nominal irc frequenc y is 12 mhz. the irc is trimmed to 1 % accuracy over the entire voltage and temperature range. problem: on lpc185x flash-based devices, the irc cu rrently has a non-linear behavior at high temperatures. this results in worse irc a ccuracy than specifi ed in the data sheet. work-around: many of the peripherals on these devices require use of an external crystal to meet timing accuracy even at the specified accuracy. the irc is typically used during boot up and during uart and can in-application programming. it is recommended to avoid use of uart and can iap at elevated temperatures to ensure accuracy.
es_lpc185x_3x_2x_1x_flash all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. errata sheet rev. 2.1 ? 23 november 2012 9 of 11 nxp semiconductors es_lpc185x/3x/2x/1x flash errata sheet lpc185x/3x/2x/1x flash-based devices [1] parameters are valid over operating te mperature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. 5. errata notes detail 5.1 n/a table 5. errata sheet spec: 2 % t amb = +55 ? c to +85 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.76 12.00 12.24 mhz table 6. errata sheet spec: 3.5 % t amb =+85 ? c to +105 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.58 12.00 12.42 mhz
es_lpc185x_3x_2x_1x_flash all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. errata sheet rev. 2.1 ? 23 november 2012 10 of 11 nxp semiconductors es_lpc185x/3x/2x/1x flash errata sheet lpc185x/3x/2x/1x flash-based devices 6. legal information 6.1 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. 6.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from competent authorities. 6.3 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners.
nxp semiconductors es_lpc185x/3x/2x/1x flash errata sheet lpc185x/3x/2x/1x flash-based devices ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 23 november 2012 document identifier: es_lpc185x_3x_2x_1x_flash please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 7. contents 1 product identification . . . . . . . . . . . . . . . . . . . . 3 2 errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 functional problems detail . . . . . . . . . . . . . . . . 4 3.1 c_can.1: writes to ca n registers write through to other peripherals. . . . . . . . . . . . . . . . . . . . . . 4 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3.2 eeprom.1: limited eeprom retention and endurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.3 mcpwm.1: mcpwm abort pin is not functional 6 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.4 pmc.1: pmc.x power m anagement controller fails to wake up from deep sleep, power down, or deep power down . . . . . . . . . . . . . . . . . . . . . . 7 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 ac/dc deviations detail . . . . . . . . . . . . . . . . . . 8 4.1 ibat.1: vbat supply current higher than expected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.2 irc.1: irc frequen cy variation higher than expected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .8 5 errata notes detail . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 n/a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 legal information. . . . . . . . . . . . . . . . . . . . . . . 10 6.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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